| 摘要 |
<p>The semiconductor memory disclosed has a pulse signal generator (9) which receives a clock signal and outputs a first pulse signal and a second pulse signal respectively as a digit line recovery control signal (RC) and a word line selection signal (WC). The pulse signal generator includes a first and a second delay circuit (11,12) connected in series, the first delay circuit providing a delay time for a pulse width of the recovery control signal, and the second delay circuit together with the first delay circuit providing a delay time for a pulse width of the word line selection signal. In response to the rising of clock (CLK), the pulse signal generator outputs the digit line recovery control signal and the word line selection signal. Using these signals, digit line recovery is started immediately after cell node inversion during write operation and word line is rendered non-selected after cell node is stabilized. It is possible to reduce the write cycle time by the extent corresponding to an overlap of the word line selection time and the digit line level recovery time, thus enabling the semiconductor memory to operate fast. <IMAGE></p> |
