| 摘要 |
<p>The N+1 frequency divider counter comprises a counter having a number of flip-flops, for counting from a predetermined initial value corresponding N+1, where N is a positive integer or zero, to a final value in response to a periodic clock signal having a predetermined frequency. The number of flip-flops receive a binary number corresponding to most significant bits of the predetermined initial value. A first logic circuit is coupled to the counter, for receiving the final value, and is response, providing a first control signal. A control logic circuit is coupled to the first logic circuit, for receiving the first control signal, a least significant bit of the predetermined initial value, and the periodic clock signal, and in response, causing an output clock signal to transition on a rising edge of the periodic clock signal when the least significant bit is a logic zero. The control logic circuit causes the output clock signal to transition on a falling edge of the periodic clock signal when the least significant bit is a logic one.</p> |
