| 摘要 |
<p>A FIFO buffer in which respective portions are controlled in a distributed manner is provided. In the FIFO buffer, a number of loop circuits (M1,M2,M3,M4) having delay elements are provided in which respective loop circuits are connected to one another in cascade manner. Additionally provided are a number of traffic control units (S1,S2,S3,S4,S5) for controlling the signal traffic between respective neighboring loop circuits. In the case where no signal is fed back to a traffic control unit from the output side and also a new signal is transmitted thereto from the input side, the traffic control unit transmits the new signal to the loop circuit which is on the output side. In the case where any signal is fed back to a traffic control unit from the output side and also a new signal is transmitted thereto from the input side, the traffic control unit again transmits the fed-back signal to the loop circuit which is on the output side and transmits the new signal to the loop circuit which is on the input side. <IMAGE></p> |
