| 摘要 |
Methods for making low cost, high density circuits for multichip modules using a two-layer interconnect pattern. The circuit is comprised of parallel line segments on each side of the dielectric film, orthogonal to each other to form a mesh or grid when viewed through the film. Line segments are interrupted, as required, to form signal lines connected to each other with metalized vias at appropriately selected intersections of the grid through the dielectric film. Power and ground lines are placed between the signal lines to prevent crosstalk between long parallel line segments. Power and ground lines are also appropriately connected at intersections to form co-connected mesh planes in the two surfaces. The novelty of the invention also resides in the methods of constructing the circuit, wherein circuit patterns on each side and vias are formed simultaneously in a single set of plating operations. Virtually no subtractive etching is required, making the methods environmentally friendly and very low cost. Line feature sizes approach 25 microns or smaller, with line pitch of 50 microns or smaller. Fabricated circuits can accommodate wire-, TAB-, or flip-chip-mounted components, and passive components by adhesive bonding or soldering. Because all lines are formed with additive copper, total circuit resistance is low, typically forty percent lower circuit resistance than signal lines 15 made with aluminum conductors.
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