发明名称 Iterative arithmetic processor
摘要 A mantissa XMk, which satisfies 1</=XMk<2, is fed to a mantissa process section in order that the iterative multiplication operation of normalized floating-point numbers Xk (k=0, . . . , m), written P=X0xX1xX2x0 . . . xXm, is performed. In the mantissa process section, a product represented in RB (redundant binary) number representation is stored in a register, and such a product is fed back to a multiplier without being converted into a binary number. A shifter for one-place right-shift is provided between the multiplier and the register. A converter sequentially converts each RB number stored in the register into a binary number and provides to the shifter a shift-amount signal S1 whose value varies with the result of such RB-to-binary number conversion. If a digit that is positioned upward two places from the binary point of a binary number obtained by the conversion is 0, then the value of S1 is set to 0. If such a digit is 1, then the value of S1 is set to 1.
申请公布号 US5570309(A) 申请公布日期 1996.10.29
申请号 US19940262866 申请日期 1994.06.21
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 MIYOSHI, AKIRA;HASHIMOTO, YUITI
分类号 G06F7/48;G06F7/487;G06F7/52;G06F7/544;(IPC1-7):G06F7/00;G06F7/38 主分类号 G06F7/48
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