发明名称 |
IEEE Std. 1149.1 boundary scan circuit capable of built-in self-testing |
摘要 |
An IEEE Std. 1149.1 boundary scan circuit which is capable of performing built-in self-testing includes a logic circuit, cascaded input boundary-scan cells that form an input boundary-scan register connected to input nodes of the logic circuit, cascaded output boundary-scan cells that form an output boundary-scan register connected to output nodes of the logic circuit, and a test access port system for controlling operation of the input and output boundary-scan cells. The test access port system provides a built-in self-test control signal to the input and output boundary-scan cells when executing built-in self-testing. The input boundary-scan register is reconfigurable to operate as a test pattern generator that provides test patterns to the logic circuit for a predetermined number of clock cycles upon receipt of the built-in self-test control signal. The output boundary-scan register is reconfigurable to operate as an output response analyzer that is driven by the logic circuit for the predetermined number of clock cycles upon receipt of the built-in self-test control signal. A family of input and output boundary-scan cells that can be reconfigured as a linear feedback shift register and as a multiple-input shift register is also disclosed. |
申请公布号 |
US5570375(A) |
申请公布日期 |
1996.10.29 |
申请号 |
US19950438417 |
申请日期 |
1995.05.10 |
申请人 |
NATIONAL SCIENCE COUNCIL OF R.O.C. |
发明人 |
TSAI, CHING-HONG;GUO, FANG-DIAHN;HONG, JIN-HUA;WU, CHENG-WEN |
分类号 |
G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3185 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|