| 发明名称 |
Memory circuit with stress circuitry for detecting defects |
| 摘要 |
A memory circuit is disclosed with stress circuitry for detecting data retention defects in the memory cells. The memory circuit comprises a memory cell array coupled to bit lines, an access circuit coupled to access the memory cells, and a discharge circuit coupled to stress the memory cells.
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| 申请公布号 |
US5570317(A) |
申请公布日期 |
1996.10.29 |
| 申请号 |
US19940277148 |
申请日期 |
1994.07.19 |
| 申请人 |
INTEL CORPORATION |
发明人 |
ROSEN, EITAN;MILSTAIN, YAKOV |
| 分类号 |
G01R31/28;G11C11/413;G11C29/06;G11C29/50;(IPC1-7):G11C13/00 |
主分类号 |
G01R31/28 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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