| 摘要 |
An static storage cell has 6 FETs, all of the same type. The cells are arrayed in columns that each have a pair of bit lines and rows that each have a word line. Each side of the cell has a pull down FET and a pull up FET and the two sides are interconnected to form a latch. The two nodes where the drain of one pull down FET and the gate of the other pull down FET are connected to the associated bit line through the associated one of two word pass FETs. The gates of the two pull up FETs and the two word pass FETs are connected to the word line. When the word line receives a selection voltage, the pull up FETs are enabled to conduct at a higher current level and the word pass FETs are enabled to apply the bit voltage to the associated node for a write operation or to apply the node voltage to the bit line for a read operation. At other times, the word pass FETs isolate the cell from the bit lines and the pull up FETs conduct at a sufficient current to maintain the latching operation of the cell.
|
