DRAM bit line contact

摘要

Two n-channel enhancement type switching transistors (SW) are fabricated on an active area (21a) in such a manner as to share a common drain region (23b), and gate electrodes (23d) are encapsulated in insulating wall structures (26) defining a contact hole (27) over the common drain region so as to allow a bit line (BL) to be directly held in contact through the contact hole (27) with the common drain region (23b). <IMAGE>