| 摘要 |
<p>An ancillary data processing circuit includes a clock masking circuit (16) and an OR circuit (15). The clock masking circuit (16) includes a counter (61) of 3 bits which is reset to zero by a synchronism detection signal (S), counts the number of clocks of a clock signal (CK) and outputs a count value (NK), a counter (62) of 3 bits which receives the count value (NK) as a preset value (NK) in response to an ancillary data start signal (SA) and counts down a clock signal (CP), a flip-flop (64) which is initialized in response to the ancillary data start signal (SA), reverses the level thereof in response to an overflow signal (DB) of the counter (62) and outputs a masking signal M, and a masking circuit (65) which calculates a combination logic of the masking signal (M) and the clock signal (CP) and outputs the clock signal (CP) or the zero level as a clock signal (CQ) in response to the level of the masking signal (M). The OR circuit (15) outputs a result of logical ORing of the clock signals (CK and CQ) as a read clock signal (CR). <IMAGE></p> |
