| 摘要 |
<p>Variation of an address signal is detected by an address transition detecting circuit. The trailing edge of a detection pulse ATD is delayed by a delay control circuit to generate a control signal phi with an expanded pulse width. Selection of word lines of a memory array is controlled depending upon a row address signal by a row decoder. The selected word line is activated only while the pulse period of the control signal phi . Before making the output of the row decoder into non-active state, the output of a sense amplifier is latched by a latch circuit by the control signal phi to output to an output circuit. Thus, double selection of the memory cell in transition of the drive signal of the word lines to be selected will never caused to avoid necessity of measure for double selection, and whereby shorten memory access period. <IMAGE></p> |
