| 摘要 |
A sense amplifier latching circuit for accepting signals from a monolithic memory array. The input signal from the monolithic memory is amplified, the logical sense of the input is determined and held in the latch, and the signal is translated down to current switch logic circuit levels having a capability for large fan-out and fan-in (dot or). The input to the sense amplifier latch has a grounded base clamp providing a very low impedance input in the presence of bi-polar noise current. The sense amplifier latch circuit further includes threshold tracking, temperature compensating, and power supply compensating circuits. The entire circuit includes emitter follower and grounded base circuits providing a high band width resulting in fast rise-time and low propagation delay.
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