| 摘要 |
A complementary metal oxide semiconductor (CMOS) exclusive OR gate is shown having a minimum number of devices for performing the exclusive OR function. The exclusive OR function is performed by utilizing the normal two input signals as logic indicating signals and generating a control signal which is a complement of one of the two logic signals. A different configuration results with the selection of the logic signal from which the control signal is to be generated. The capacitance of the output node or output signal is charged by any one of a plurality of current paths associated with each logic configuration.
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