发明名称 |
Synchronous semiconductor memory device with a write latency control function |
摘要 |
A semiconductor memory device for processing data in synchronization with a system clock applied from the exterior includes a circuit for generating a write latency control signal, a circuit for generating one active information enlarged signal from a plurality of active information signals generated in response to a column related control signal supplied from the exterior, and a circuit for holding internal operations of a column address counter, a burst length counter and a data transfer switching circuit for a prescribed time in which the active information enlarged signal is in an active state.
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申请公布号 |
US5568445(A) |
申请公布日期 |
1996.10.22 |
申请号 |
US19950397690 |
申请日期 |
1995.03.02 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
PARK, CHUROO;LEE, SI-YEOL;LEE, HO-CHEOL;JANG, HYUN-SOON |
分类号 |
G11C11/407;G11C7/22;G11C11/408;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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