| 摘要 |
<p>PURPOSE: To reduce skew between clock signals of different frequency dividing ratios into which a single reference clock signal is frequency-divided. CONSTITUTION: Clock signals CK11 and CK12 of frequency dividing ratios (1/1) and (1/2) into which a reference clock signal CK is frequency-divided occasionally rise in logical state at the same original timing although their frequencies are different. However, the real timing of such rising of logical state is mutually deviated by the dispersion of the circuit and skew is generated. By temporarily turning on a clock signal synchronizing switch SW1 for the period including such rising timing, the rising skew between these clock signals CK11 and CK21 which are originally equal to each other is reduced.</p> |
