| 摘要 |
PURPOSE: To provide a PLL type angle modulation circuit for which a problem such as jitter is improved. CONSTITUTION: An information signal s(t) is supplied from an input terminal 1 to an adder circuit 2, added with an error signal Er(t) outputted from a loop filter 12, and supplied to a VCO 3. A modulated output F(t), whose angle is modulated by the information signal s(t), is outputted from the VCO 3. The modulated output F(t) is outputted to an output terminal 13 and supplied to a frequency divider 4 having a number N1 of frequency division. A frequency divided output F(t)/N1 is made into multiple phases through a multiphase signal generating circuit 5 and plural frequency divided outputs of different phases are outputted and supplied to phase comparators 8-10. On the other hand, a reference signal from a reference signal oscillator 6 is passed through a multiphase signal generating circuit 7 and plural reference signals of different phases are generated and supplied to the phase comparators 8-10. The phase compared output signals are added by an adder circuit 11 and supplied to the loop filter 12, and the error signal Er(t) is provided and supplied to the adder circuit 2. |
