| 摘要 |
A decoder is disclosed for an input delay modulation information signal in which a transition occurs at the center of a bit cell containing a "1" and a transition occurs at the boundary between two successive bit cells containing "0s." The polarities of the information signal a quarter of a bit cell prior to and a quarter of a bit cell following the center of a bit cell are compared and a first decoded signal is generated when the polarities are different. The polarities of the information signal at the beginning and end of a bit cell are compared and a second decoded signal is generated when the polarities are different. The first and second decoded signals are applied to an "and" gate to produce an NRZ output signal.
|
