| 摘要 |
<p>PROBLEM TO BE SOLVED: To facilitate a contact hole forming process and reduce chip size, by uniformly maintaining active region in overall cell by forming a second active line on an active region for the contact hole. SOLUTION: A main source line is connected to a source line 35 through a common contact hole 39, and a plurality of first active lines 41 are positioned under and parallel to bit lines, while including a memory cell, and a source, a drain and a channel of a selected transistor. Each first field separating line 49 is positioned parallel to and in the intermediary of each first active line 41. A second active line 37 is connected perpendicular to the source line 35, and positioned parallel to and under the main source line. Each second field separating line 51 is formed parallel to and in the intermediary of each first active line 41 and each second active line 37.</p> |
