PLL CIRCUIT

摘要

PURPOSE: To delay the transient response characteristic to the output phase variance caused in a switching mode of a reference signal in a simple constitution and to fast response to the minute variance caused in a steady mode. CONSTITUTION: The output of a voltage control oscillator 7 is divided by a frequency divider 8 in accordance with the frequency of an input reference signal. A phase comparator 5 compares the phases with each other between the divided outputs and the input reference signal. This phase error signal is converted into the control voltage of the oscillator 7 by a PLL circuit through a loop filter 6. Then the voltage that is equal to the output voltage of the filter 6 in terms of DC is generated to the PLL circuit. The transient response characteristic of the generated voltage is set slower than the response characteristic of the output voltage of the filter 6 in a buffer circuit 21. Then a limit circuit 23 limits the output of the filter 6 when the voltage difference between the output of the circuit 21 and that of the filter 6 exceeds a prescribed voltage level.