| 摘要 |
<p>PURPOSE: To reduce the variance of phase matching accuracy in consideration of the operating conditions of both best and worst states by varying the changing width of the delay value of a delay chain. CONSTITUTION: In a delay chain 14, a system clock CK1 is inputted to an inverter of the first stage as an input. Then a prescribed delay value is selected based on the output of an up/down counter 13, and an intra-chip clock CK2 is generated. In such a way, the delay value varies in the chain 14 and the matching of phases is secured between both clocks CK1 and CK2 based on the prescribed delay value that is extracted out of the chain 14. In other words, the changing width is variable, e.g. gradually increased for the delay value of the chain 14. As a result, the variance of phase matching accuracy can be minimized even when a process varies in the best and worst states.</p> |
