发明名称 TEMPORARY DATA MEMORY
摘要 PURPOSE: To provide a temporary data memory which can be applied to a digital VTR by decreasing the number of times for accessing a DRAM without requiring any extra memory for error correction or other correction. CONSTITUTION: A first error correction means 12 outputs a data block affixed with a correction result code. A row address access means 141 accesses the row address on a DRAM 11 based on an identification number associated with the data block. Management data 54 generated from management data generation means 53 and written in the DRAM 11 is read out by the row address access means 141 and the column address initial value of a data block memory area 13 to be accessed is generated by a column address initial value generating means 142. A continuous column address access means 143 then accesses continuous column addresses and reads the data block in the DRAM or writes the data block.
申请公布号 JPH08273347(A) 申请公布日期 1996.10.18
申请号 JP19950073390 申请日期 1995.03.30
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SATO MASASHI;FUJII SHOZO
分类号 G11C7/00;G06F11/10;G11B20/18;G11C11/401;H03M13/29;H04N5/907;(IPC1-7):G11C7/00 主分类号 G11C7/00
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