| 摘要 |
<p>PURPOSE: To provide a semiconductor memory in which analysis of defective bit line is facilitated. CONSTITUTION: The semiconductor memory comprises a memory cell array 11 in which memory cells are arranged at each intersection of a word line WL and a bit line BL, a word line select circuit 12 for driving the word line selectively, a column select circuit 13 for selecting the bit line, and a sense amplifier circuit 14 for reading out a data from a selected bit line. A circuit 16 for detecting the potential level of a bit line under deselect state is provided at the end of the bit line BL of the memory cell array 11 opposite to the sense amplifier circuit 14. An auxiliary column select circuit 15 is also provided in order to connect a deselect bit line contiguous to a bit line selected by the column select circuit 13 with the level detection circuit 16.</p> |
