ROW REDUNDANCY CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE

摘要

Disclosed is a redundancy for replacing a memory cell with a predetermined defect with additional spare cells in a semiconductor memory device in which spare word lines dependent upon a certain submemory cell array among a plurality of submemory cell arrays and fuse boxes independently arranged while being free from the position of said plurality of submemory cell arrays are provided. Thus, the redundancy operation is performed in the submemory cell array having the spare word lines by a program of the fuse boxes, thereby capable of maximizing the efficiency of the redundancy along with the trend to achieve high integration of a chip, being optimally applied to the layout of the chip, repairing word-line fails occurring in different normal submemory cell arrays by using the word lines of one spare array, and sufficiently managing plural word-line fails in the normal memory array.