Ferroelectric memory sensing scheme

摘要

In a ferroelectric memory cell having a plate line, a word line, and a bit line, the bit line being coupled to a sense amplifier, a sensing method comprises biasing all N-wells in the sense amplifier to a voltage greater than the most positive voltage excursion of the bit line. The latter is precharged to a logic one voltage, and the word and plate lines are set to an initial logic zero voltage. The word line is stepped from the initial logic zero voltage to the logic one voltage, and the plate line is stepped from the initial logic zero voltage to the logic one voltage. The sense amplifier is activated to resolve voltage developed on the bit line to a full logic voltage while the word and plate lines are at the logic one voltage, and the word and plate lines are returned to the initial logic zero voltage.