| 摘要 |
a first logic means (A1,A3,A5) for inputting the first input which are the input signals (VA, VB, Vc) transmitted from a CPU, generating an error by detecting the system signal, and inputting the second input as a generating stop signal; a second logic means (A2,A4,A6) for inputting it as the first input the respective signals inverted the input signals transmitted from the CPU, and inputting the second input which is the stop signal; a dividing and delaying means (M1, M2) for dividing it into four the output signal of the logic means (A1, A2, A3, A4, A5, A6), and simultaneously delaying it according to a clock frequency; and a third logic means (N1-N6) for respectively inputting the first input which is respective output signals of the logic means (A1, A2, A3, A4, A5, A6), respectively inputting the second input which is respective output signals of the dividing and delaying means (M1, M2), and not generating simultaneously an OFF signal.
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