CONTROL TRANSISTOR STRUCTURE OF EEPROM CELL

摘要

a buried impurity layer(2) to form a source and a drain on an active region of a semiconductor substrate(1); a gate oxide(3); a tunnel/window(4) formed by etching the gate oxide(3) on top of the drain; a first polysilicone layer(5) formed by filling the T/W(4); a first ONO layer(6) formed to surround the first polysilicone layer(5); a second polysilicone layer(7) formed on the first ONO layer(6); a second ONO layer(8) formed on top of the second polysilicone layer(7) and contacted to the first ONO layer(6); a floating gate(FG) formed with a third polysilicone(9) contacted to the first polysilicone(5); a third ONO layer(10) formed to surround the third polysilicone(9); a fourth polysilicone(11) formed through the second polysilicone(7), the second and the third ONO layer(8); and a control gate(CG) formed with the second and the fourth polysilicone(7,11).