| 摘要 |
A lost data correction circuit has a multiplication unit MLT having one dividing unit DIV performing division based on the Euclidean mutual division method, 4t (t is the number of symbols for which the error can be corrected and 2t is the number of the parity symbols) number of computation units PE and (8t+2) number of registers A and B provided in parallel. In this circuit, as the first stage, the lost data positions U are calculated from the error flags and the syndromes S are calculated from the received code; and then, as the second stage, the lost data position polynomial u and correction syndrome T are simultaneously calculated in epsilon steps ( epsilon is the number of the lost data symbols); as the third stage, the error evaluation polynomial omega and error position polynomial sigma and the corrected error position polynomial +E,uns sigma +EE thereof are calculated in (2t- epsilon ) steps; as the fourth stage, the product polynomial UxX of them is calculated; and as the fifth stage, the error positions are calculated. That is, in this lost data correction circuit, the total error position polynomial and error evaluation polynomial are calculated in two steps.
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