| 摘要 |
A semiconductor device and process for making the same which reduces capacitance between adjacent conductors on a connection layer, reduces overetching due to via misalignment or uneven device topography, and maintains a rigid structure with good heat transfer characterisitics. In one embodiment, horizontal gaps between the patterned conductors 18 and 44 are substantially filled with an organic-containing dielectric material (Allied Signal 500 Series, for example) 22 and 54. Inorganic dielectric layers 24 and 56 are formed over organic-containing dielectric layers 22 and 54, respectively, from a material such as silicon dioxide. Vias are etched through the inorganic dielectric layers using an etch process such as fluorocarbons in a high density plasma which does not appreciably etch the organic-containing dielectric material.
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