NO DELAY CHANNEL ARRANGEMENT CIRCUIT

摘要

a decoding means 30 for outputting the decoded signal by inputting a control signal; a latch means 31 for inputting the multiplexed input signal heat by simple byte-interleaving, latching the input signal according to an enable signal as the output of the decoding means 30, and outputting the demultiplexed signal; a channel detecting means 32 for searching any channel cognitive identification number according to the input, and generating a detecting pulse; an adder means 33 for inputting a lower predetermined bit among input signals of the channel detecting means 32 and an inner set initial value, and adding and outputting two input signals; and a counting means 34 for operating the predetermined initial value at the beginning, loading the output of the adder means 33 into the initial value when inputting the detecting pulse from the channel detecting means 32 and supplying a control signal into the decoding means 30.