| 摘要 |
A synchronized semiconductor memory device comprises a memory cell array, an address input circuit, an address set circuit, a command input circuit, a data reading/writing control circuit, a data output circuit, a data input circuit, a clock input circuit, an internal clock generating circuit, and an internal clock timing control circuit. The internal clock timing control circuit includes a delay circuit to receive a reference internal clock generated in the internal clock generating circuit, a plurality of level signals set in accordance with a given mode register set cycle, and a plurality of row address enable signals, and for generating at least an internal clock signal for timing-controlling the data reading/writing circuit. The internal clock timing control circuit also includes a logic circuit to receive the reference internal clock generated in the internal clock generating circuit and the plurality of row address enable signals, and for generating another internal clock signal for timing-controlling the data input circuit.
|
