发明名称 METHOD FOR OMISSION OF BUS TURNAROUND CYCLE AND COMPUTER SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To perform the allocation of a bus at a high speed in the case of being related to read data bus stationed time when the same slave is continued or write data bus stationed time when the same master and slave are continued. SOLUTION: New selectable signals are added to a bus interface and called as final transfer confirmation notice signals and the signals are received by the arbiter of a system bus 12. In the case that the present data stationed time and the next data stationed time are both read operations to the same slave (of a memory controller or the like) or write operations from the same master to the same slave, the arbiter allows to turn a data bus 121 to the master of the next data stationed time in a cycle following the claim of a final transfer confirmation notic indicator. Thus, the arbiter can allow the use of the bus one cycle earlier than normal time. Thus, a bus turn-around cycle is omitted and a data bus band width is increased for the maximum of 20%.</p>
申请公布号 JPH08263430(A) 申请公布日期 1996.10.11
申请号 JP19950316616 申请日期 1995.12.05
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 JIYON SUTEFUAN MUHIKU;RONARUDO ZABIAA AROOYO;CHIYAARUZU GOODON RAITO;ROORENSU JIYOSEFU MAAKERU
分类号 G06F15/16;G06F9/52;G06F13/28;G06F13/30;G06F13/362;G06F15/177;G06F15/78;(IPC1-7):G06F13/362;G06F15/163 主分类号 G06F15/16
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