发明名称 MEMORY INTERFACE CIRCUIT
摘要 <p>PURPOSE: To take full advantage of the merit of the memory size reduction of a non-distribution type MLS method by converting the input data signal corresponding to a single scanning into the signal corresponding to dual scannings, securing the driving margin of liquid crystal while maintaining the compatibility with conventional inferfaces and making the memory size required for storing display data half as much as the memory size required in an AA method and a distribution type MLS method. CONSTITUTION: In a memory interface circuit 100, a memory 1 having a memory size capable of storing the input data signal equivalent to one display screen of a liquid crystal panel 9 and a control circuit 2 controlling so that the input data signal corresponding to the one display screen is written in the memory 1 by a single scanning and the signal is read out in accordance with the upper screen part 9a and the lower screen part 9b by dual scannings are provided and the readout timing of the lower screen part 9b is made so as to be delayed by the period being about half as long as one frame period of the write signal with respect to the readout timing of the upper screen part 9a.</p>
申请公布号 JPH08263015(A) 申请公布日期 1996.10.11
申请号 JP19950069988 申请日期 1995.03.28
申请人 SHARP CORP 发明人 FURUKAWA HIROYUKI;YAMAMOTO KUNIHIKO
分类号 G02F1/133;G09G3/20;G09G3/36;G11C7/00;(IPC1-7):G09G3/36 主分类号 G02F1/133
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