发明名称 CLOCK GENERATING CIRCUIT FOR LAMINATED INTEGRATED CIRCUIT
摘要 PURPOSE: To prevent a rising signal and a trailing signal of bi-phase clock signals fed to any of integrated circuit layers A-C of the laminated integrated circuit from being overlapped with each other. CONSTITUTION: A couple of clock shaping means 3, 4, and buffer drive means 5, 8 receiving an output of the clock shape means respectively are formed into one layer B of the laminated integrated circuit. Then buffer means 9-14 delivering each output of the buffer drive means 5, 8 to a load and the means 6, 7, 21-24 feeding back an output of each buffer drive means to other clock shape means are formed to each layer of the laminated integrated circuit. No H output is obtained from a NOR circuit being the clock shape means (that is, the other clock does not rise) before outputs fed back to the NOR means being the clock shape means are all not at a low level (that is, one clock does not trail at any layer).
申请公布号 JPH08265119(A) 申请公布日期 1996.10.11
申请号 JP19950091409 申请日期 1995.03.24
申请人 FUJI XEROX CO LTD 发明人 TAGUCHI MASAHIRO;MIYAGAWA NOBUAKI;KOYANAGI MITSUMASA
分类号 H03K5/151;H03K3/02 主分类号 H03K5/151
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