| 摘要 |
<p>PURPOSE: To improve integration by constituting multi-bit information stored in plural memory elements so as to take out it time-sequentially and continuously, and reducing the number of word lines. CONSTITUTION: A word line WL1 is provided in common for memories TRT1 -T8 , drains of each TR are connected in common to a bit line BL1 , and sources are connected in common to a source line SL. A delay circuit DL consisting of plural series resistors R1 -R7 is connected to the word line WL1 , and connecting points of each resistor are connected to gates of each memory transistor. Access signals supplied from the word line WL1 are successively delayed and given to gates of memory TRs, stored contents are successively read out, and a current value is detected by a sense amplifier SA. Thereby, word lines are reduced, and a memory cell area can be reduced.</p> |
