发明名称 |
BUS TRACE DEVICE AND METHOD |
摘要 |
PURPOSE: To provide a bus trace device of high performance which can eliminate the discontinuation of the system operation in a fault detection mode and the change of the circuit constitution that is required in response to the fault detection mode by using a bus trace function that is connected to the system and adaptive to the different fault detection modes. CONSTITUTION: A bus trace device is connected to a system bus 2 and traces the bus information necessary for detection of faults. Then the bus trace device is provided with a trace memory 13 of large capacity consisting of a DRAM of a double memory block system and a fast trace memory 14 which serve as the trace memories that store the trace data. A bus trace control circuit 15 controls the trace operations and also controls the write operations of both memories 13 and 14 in accordance with the trace start/stop conditions that are set by an SVP 4. |
申请公布号 |
JPH08263328(A) |
申请公布日期 |
1996.10.11 |
申请号 |
JP19950062982 |
申请日期 |
1995.03.22 |
申请人 |
TOSHIBA CORP |
发明人 |
KIKUCHI SHIGEMASA;KIHARA JUNICHI |
分类号 |
G06F11/34;G06F11/00;G06F11/22;G06F11/28;G06F11/30;G06F13/00 |
主分类号 |
G06F11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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