VARIABLE DELAY CIRCUIT AND TIMING SIGNAL GENERATING CIRCUIT

摘要

A variable delay circuit which is reduced in size and improved in operating speed, and a timing signal generating circuit which generates high-resolution and high-accuracy timing signals are disclosed. A variable delay element comprises a P-channel and N-channel dual gate MOSFETs, in which an input signal is fed to the first gates, a control voltage (Vcp) for changing the transition time of the output waveform is applied to the second gate of the P-channel MOSFET, a control voltage (Vcn) is applied to the second gate of the N-channel MOSFET and the output signal is outputted from the common drains. A phase-locked loop circuit (100) is composed of a variable delay circuit (120) comprising cascade-connected variable delay elements, a phase comparator (140) which compares the phase of the output signal (e1) of the circuit (120) with that of a CLK signal (e2), and a feedback circuit (150) which feeds back the output of the comparator (140) to the variable delay circuit (120). A timing signal selecting circuit section (200) is constituted of a synchronous delay circuit (110) which outputs a signal representing the high-order digits of delayed data at a rate which is an integral multiple of the CLK frequency a decoder (160) which decodes the low-order digits of the delayed data, and a selector circuit (130) which selects one of the outputs of (m) variable delay elements based on the output signal of the circuit (110) and selects signal of the decoder (160).