| 摘要 |
An improved method for fabricating a semiconductor structure which may contain, for example, bipolar and CMOS devices, is disclosed which overcomes problems in the art. A method in accordance with one embodiment of the present invention may be used to self-align P+ isolation regions (28), P-wells (24), P-type base regions (34), and N+ collector contacts (38). In this improved method, the P+ isolation regions, P-wells, P-type base regions, and N+ collector contacts are defined using a single masking step (20) and are thus automatically self-aligned. Since this self-alignment eliminates several critical mask alignments (and hence several alignment tolerances), valuable die area is conserved, thereby allowing for increased component density.
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