发明名称 |
A parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system |
摘要 |
<p>A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor. Each data processor has a writeback buffer for storing the data block previously stored in a victimized cache line until its respective writeback transaction is completed and an Nth+1 Dtag for storing the cache state of a cache line associated with a read transaction which is executed prior to an associated writeback transaction of a read-writeback transaction pair. Accordingly, upon a cache miss, the interconnect may execute the read and writeback transactions in parallel relying on the writeback buffer or Nth+1 Dtag to accommodate any ordering of the transactions. <IMAGE></p> |
申请公布号 |
EP0735485(A1) |
申请公布日期 |
1996.10.02 |
申请号 |
EP19960302062 |
申请日期 |
1996.03.26 |
申请人 |
SUN MICROSYSTEMS INC. |
发明人 |
NISHTALA, SATYANARAYANA;EBRAHIM, ZAHIR;VAN LOO, WILLIAM C.;LOWENSTEIN, PAUL;LEE, SUE KYOUNG;COFFIN III, LOUIS F., |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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