发明名称 |
Halbleiteranordnung zur Verbesserung der Hochfrequenzcharakteristiken und zur Vermeidung von Rissen im Chip |
摘要 |
<p>A semiconductor device comprises a plurality of gate electrodes (14), drain electrodes (5), and source electrodes (11), axi-symmetrically formed on opposite sides of a gate pad (12) and drain pad (4). Two source pads (9, 10) are arranged at the ends of these electrodes, to which the source electrodes are connected, so that a gate width (WW) can be shortened. Therefore, an output power, gain, etc., can be increased, and the high-frequency characteristics can be improved. Further, when arranging a plurality of semiconductor devices in parallel, the semiconductor chip can be formed in the shape of a square, i.e., the aspect ratio thereof can be reduced, therefore, cracks in the semiconductor chip (semiconductor device) can be avoided. <IMAGE></p> |
申请公布号 |
DE69213032(D1) |
申请公布日期 |
1996.10.02 |
申请号 |
DE1992613032 |
申请日期 |
1992.01.03 |
申请人 |
FUJITSU LTD., KAWASAKI, KANAGAWA, JP;FUJITSU YAMANASHI ELECTRONICS LTD., YAMANASHI, JP |
发明人 |
KOJIMA, MASAKAZU, C/O FUJITSU LIMITED, KAWASAKI-SHI, KANAGAWA 211, JP;AOKI, YOSHIO, C/O FUJITSU LIMITED, KAWASAKI-SHI, KANAGAWA 211, JP;SANO, SEIGO, C/O FUJITSU YAMANASHI ELECTRONICS, NAKAKOMA-GUN, YAMANASHI 409-38, JP |
分类号 |
H01L21/3205;H01L21/338;H01L23/52;H01L29/417;H01L29/423;H01L29/812;(IPC1-7):H01L29/423 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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