| 摘要 |
PURPOSE:To reduce the area of a chip, to fine an element and to improve latch- up resistance by forming a groove to a semiconductor substrate, shaping a conductor having low-resistance through an insulating film formed on the inner wall of the groove and applying bias potential to a well to the conductor. CONSTITUTION:A P well 22 and an N well 23 are each formed partially to the surface of a substrate 21, and two grooves 24, 25 reaching to the substrate 21 are shaped to a boundary section between both wells. An oxide film 26 is formed to the whole surface containing the insides of the grooves, and the oxide film 26 is removed selectively to leave oxide films 26'. Photo-resist films 27 are removed, and Mo layers 28 as a terminal Vss and a terminal Vcc are buried through the residual oxide films 26'. Gate electrodes 29, 30 are each shaped on the P well 22 and the N well 23, and N<+> source and drain regions 33, 34 are formed to the surface of the P well 22 and P<+> type source and drain regions 35, 36 to the surface of the N well 23. An inter-layer insulating film 37 is removed selectively, contact holes 381-384 are shaped and leading-out wirings 391-394 are formed, thus manufacturing a CMOS transistor consisting of an NMOS transistor and a PMOS transistor. |
