| 摘要 |
<p>The logic circuit has an input node for receiving an input signal which is variable between first and second input logic levels. An output node produces an output signal which is variable between two output logic levels. A clock node receives a clock signal adiabatically varying between two potentials, the clock signal defining a first period during which the clock signal adiabatically changes from the first potential to the second potential and a second period during which the clock signal adiabatically changes from the second potential to the first potential. A first path between the clock node and the output node permits the output signal to adiabatically follow the change of the clock signal from the first potential to the second potential when the input signal is at the first input logic level until the output signal reaches the second output logic level. The output signal remains at the second output logic level as long as the input signal is at the first input logic level, regardless of any further change by the clock signal. A second path between the clock node and the output node permits the output signal to adiabatically follow the change of the clock signal from the second potential to the first potential when the input signal is at the second input logic level until the output signal reaches the first output logic level, the output signal remaining at the first output logic level as long as the input signal is at the second input logic level, regardless of any further change by the clock signal.</p> |
