发明名称 |
Clock phase shifting method and apparatus |
摘要 |
A circuit for providing a phase controlled clock output includes a ring oscillator having a delay line for providing an internal clock signal whose period varies with on-chip variations due to temperature, voltage, and process. The circuit also includes a clock phase select circuit having a counter and divider for determining the number of delays in one external clock period and an input for a phase select value. A delay line having delay elements similar to those of the ring oscillator provides multiple delayed clock signals from the reference clock signal. A multiplexor having odd and even sides is used to select the desired clock signal in a glitchless manner. The phase controlled clock signal output is controlled by the phase select signal and is compensated for on-chip variations due to temperature, voltage, and process.
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申请公布号 |
US5561692(A) |
申请公布日期 |
1996.10.01 |
申请号 |
US19930163643 |
申请日期 |
1993.12.09 |
申请人 |
NORTHERN TELECOM LIMITED |
发明人 |
MAITLAND, ROGER J.;IRELAND, HAL H. |
分类号 |
H03K5/13;H03K5/135;(IPC1-7):H04L7/027 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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