| 摘要 |
PROBLEM TO BE SOLVED: To reduce a tact time by half and to provide a TFT substrate which is prevented from deteriorating in electrical properties and adhesive power by a method wherein a fine amorphous silicon layer formed at a low deposition rate, a fine amorphous silicon layer formed at a high deposition rate, and a coarse amorphous silicon layer formed at a high deposition rate are included. SOLUTION: A fine amorphous silicon layer 32 formed at a low deposition rate laminating on a gate insulating film 2 and a coarse amorphous silicon layer 31 formed at a higher deposition rate than the fine amorphous silicon layer 32 are included. For instance, a fine amorphous silicon layer 32 excellent in electrical properties and formed at a rate of 70 500Å/min is evaporated on a gate insulating amorphous nitride film 2 as thick as 50 to 500Å. A coarse amorphous silicon layer 31 formed at a rate of 150 to 1000Å/min and excellent in physical-mechanical characteristics is evaporated as thick as 1000 to 1500Åor so.
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