| 摘要 |
<p>PURPOSE: To attain a high speed operation with low power consumption by turning on/off a FET receiving a clock signal of a differential flip-flop circuit so as to eliminate the need for a high power supply voltage. CONSTITUTION: A clock signal is fed to the gates of enhancement FETs 7, 8 connecting to a source of each enhancement FET of a NOR circuit comprising a depletion FET 1 and enhancement FETs 2, 3 as load elements and a NOR circuit using depletion FETs 4, 5, 6. Then the FETs are formed to be a latch to on/off. Thus, one stage of critical path gate is enough and then high speed operation is attained, a current source FET of a differential FF is not required and no high voltage power supply is required. Furthermore, no level shift circuit is required for data storage and low power consumption is attained. Moreover, LSI is adopted for basic circuits, then the circuit is operated at a high speed with a low voltage power supply.</p> |
