| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a run length decoding device which reduces hardware burdens without using a buffer that needs a complicated interface circuit. SOLUTION: This device includes an address generator 10 which receives run data and generates a write address, a counter 14 that generates a read address, 1st and 2nd memory 28 and 30 which store level data and generate a decoded video signal, a T flip-flop circuit 12 which generates 1st and 2nd selection signals, 1st and 2nd MUXs 16 and 18 which generate write and read addresses in response to the 1st and 2nd selection signals, an inverter 20 that inverts an input signal and supplies an inverted signal to the memory 28, three- state gates 22 and 24 which selectively supply level data LEVEL to the memory 28 and 30 and a 3rd MUX 26 which selects and outputs a decoded video signal.</p> |
