发明名称 SWEEP-AND RANGE-DELAY CIRCUIT
摘要 <p>PURPOSE: To provide a sweep-delay circuit in which an arbitrary delay amount can be obtained with a simple constitution. CONSTITUTION: The write address of a sweep memory part 8 is generated by a write-sweep-address generation part 1 and by a write-range-address generation part 4. By a read-sweep-address generation part 3 and by a read-range- address generation part 6, a delay amount which has been set by a sweep-delay amount setting part 2 and by a range-delay setting part 5 is subtracted from the write address so as to find a read-sweep-address and a read-range-address, and the read address of the sweep memory part 8 is found. As a result, a required sweep- and range-delay amount can be obtained.</p>
申请公布号 JPH08248123(A) 申请公布日期 1996.09.27
申请号 JP19950079323 申请日期 1995.03.13
申请人 NIPPON AVIONICS CO LTD 发明人 MOCHIZUKI ATSUHIRO;FUKUDA KOICHI
分类号 G01S7/285;G01S7/298;(IPC1-7):G01S7/285 主分类号 G01S7/285
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