发明名称 MULTICHIP MODULE PACKAGE
摘要 PROBLEM TO BE SOLVED: To reduce the vertical dimension, that is, the thickness of a multichip module package by a method, wherein a cavity part is provided in a printed- wiring board to arrange efficiently an MCM tile in the cavity part. SOLUTION: A silicon on silicon MCM tile 17, which consists of a silicon substrate 18 and silicon chips 19 and 20, is arranged in a cavity part 16 formed in a PW board 11, which has lower, middle and upper levels 12, 13 and 14. A wire-bonding finger 21 on the substrate 18 is interconnected with a contact pad 23 on the level part 13 of the board 11 via a wire 22. Whereupon, the cavity part 16 is sealed with a structural member. An adaptable capsule-shaped sealing material, which wraps the chips of the tile 17 therein, is made to fill the part 16. Thereby, the thickness of an MC package can be reduced, and a minimization of a system and a device, which adopt the package, becomes possible.
申请公布号 JPH08250652(A) 申请公布日期 1996.09.27
申请号 JP19960036034 申请日期 1996.02.23
申请人 AT & T CORP 发明人 INON DEGANI;TOOMASU DEIKUSON DEYUDARAA;BIYUNGU JIYOON HAN;ARAN MAIKERU RIONZU;KINGU RIEN TAI
分类号 H01L25/18;H01L23/13;H01L23/14;H01L23/24;H01L23/367;H01L23/538;H01L25/04;H01L25/065;H01L25/07;H01L25/16;H05K1/14;H05K1/18 主分类号 H01L25/18
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