| 摘要 |
<p>PURPOSE: To provide a system verification device and system verification method which perform simulation based upon abstract input data. CONSTITUTION: An equation expressing the design of a system is inputted by using a design input means 1. A data input means 2 is used to input input data to a system and simulation data including a couple of output data expected to be outputted from the system in response to the input data by using terms containing only variables. A verification means 3 calculates the output value from the system which is based upon the input data by performing simulation by term rewriting on the basis of a specific term rewriting rule corresponding to the equation, input data, and elements of the design, and verifies whether or not the output value matches with the expected output data. An output means 4 outputs the result of the verification.</p> |
