| 摘要 |
PURPOSE: To provide the clock signal generation circuit which doesn't require a control system and is free from the momentary break or the phase variance of an output clock signal regardless of the loss of n-1 other input clock signals in the case that arbitrary one of n input clock signals is normal CONSTITUTION: Plural differential receivers 11 to 1n each of which differentially receives a pair of clock signals synchronized with each other, wired operation circuits 31 to 3n and 41 to 4n which add respective outputs of these differential receivers on a transmission line after AC coupling, a filter 5 which limits the bands of outputs of these operation circuits, and an output buffer 6 which discriminates and outputs the output waveform of this filter are provided. |
