| 摘要 |
<p>PURPOSE: To suppress the current consumption i0 accordance with the reduction of the operation clock frequency of a CPU while securing the normal operation on the peripheral circuit side at the time when the operation clock frequency or the CPU is reduced to reduce the current consumption. CONSTITUTION: The operation clock frequency switched in accordance with the access state to a CPU 104 is detected, and a decoder part 103 designates the operation frequency mode of the CPU correspondingly to the detected operation clock frequency by a mode 10 signal. Then, a timing circuit part 102 generates plural timing signals, which normally operate a peripheral circuit 106, in accordance with the designated operation frequency mode, and a shortening control part 102A shortens the active time of each generated timing signal based on the operation frequency mode to generate the timing signal of each mode and outputs it to the peripheral circuit 106.</p> |
